A latch array or matrix is widely used in applications that depend on SRAM latches for their operation, the most common being flash memories, Complex Programmable Logic Devices (CPLDs) and FPGAs. A latch array consists of a finite number of latches with each latch storing a unique bit. There are signals and structures associated with a latch array for group control of the latches. One such signal can set/reset the latch array. Referring to FIG. 1, the most conventional way of providing an initialization signal to the latches is through a pass transistor 2 connected to every latch 1. Basic latch construction of back-to-back 1a & 1b connected inverters is shown. The gates of the pass transistors 2 are tied together and a common set/reset signal 3 drives them.
Another known method of initializing the latches requires the use of an addressing or decoding scheme to access the latches individually or in groups. During the access cycle, the latches visible to the configuration data frame are loaded with the set/reset bit. This approach requires many clock cycles to initialize the latch array.
U.S. Pat. No. 6,301,173 B2 describes another technique for improving the speed of resetting of a latch array. However, this technique requires additional hardware in the form of bit line clampers, short-circuits and transfer control circuits to be added for each bit line pair, thereby making the size of the latch array significantly bigger.